Highlights
- 10+ years of experience in both industry and academia, specialised in hardware architecture design for machine learning.
- Googler, ex-Samsung, ex-Intel.
- PhD from Imperial College London, with full scholarship.
- Author of over 30 publications and patents.
- Serving as member of program committees (FCCM, ASAP, and PACT), program chair (ARC 2022) and reviewer (NeurIPS, ICLR, ICML, AAAI, TCAS, and TOMPECS).
I am currently a TPU architect at Google, where I define the next-generation machine learning accelerator architecture and ISA for on-device machine learning applications. Previously, I was an NPU architect at the startup Neubla, leading the architectural and ISA development. Before that, I served as a senior research scientist at Samsung AI Centre in Cambridge, focusing on the co-design of hardware and deep neural networks. My earlier experience includes roles at Altera/Intel and in the Research and Development Department of ARM.
I obtained my PhD in Computing at Imperial College London in 2014, under the supervision of Professor Wayne Luk. Before that, I received my BEng and MPhil degrees in Computer Science and Engineering from the Chinese University of Hong Kong, in 2008 and 2010, respectively. My research was about FPGA acceleration of sequential Monte Carlo method (particle filter) and Proximity Query process. See my publications, DBLP list and Google Scholar Citations for details.
Specialties
- Hardware architecture for machine learning
- Hardware-aware neural architecture design
- Embedded real-time control applications in industrial, automotive and energy industries
More about me
- A Croucher Scholar (My interview article).
- Running The Chinese University of Hong Kong Alumni Association, UK.
- Love basketball and outdoor fitness training.
About my Chinese name
- Written: 周俊邦
- Cantonese Romanisation: Chau Chun Pong
- Mandarin Romanisation: Zhou1 Jun4 Bang1
*In Chinese naming order, the family name comes first, followed by the given name.